This invention relates to binary multiplier systems and, in particular to such multiplier systems which are adapted for use in a Finite Impulse Response (FIR) digital filter arrangement.
In U.S. Pat. No. 4,486,851, entitled "Incrementing/Decrementing Circuit for a FIR Filter" and in U.S. Pat. No. 4,507,725, entitled "Digital Filter Overflow Sensor", each of which patents were granted to L. A. Christopher and D. L. Sprague, a finite impulse response filter is described. Additional details of such an arrangement are also provided in the 1982 Master's Thesis submitted by Christopher to MIT (Massachusetts Institute of Technology) entitled "A Versatile FIR Filter for Use in the Video Processing Section of a Digital Television Receiver". In the Christopher and Sprague FIR filter arrangement, a plurality of specifically delayed signal samples are multiplied by predetermined coefficients and the resulting products are summed to provide the desired filter characteristic. The multiplication and summing functions are performed in that FIR filter making use of shift matrix and adder circuits designed to function with two's complement arithmetic. Christopher and Sprague recognized that simplification of the arithmetic operations is particularly desirable in an FIR filter in order to minimize circuit complexity and to maximize computational speed. To that end, Christopher and Sprague employed arrangements for truncating the partial product outputs of their multiplier circuits to eleven bits where eight bit multiplicand and canonical signed digit (CSD) multiplier quantities were employed. Furthermore in performing two's complement multiplication, Christopher and Sprague only simulated or approximated the steps required to convert the truncated partial products to two's complement form. Christopher et al supplied sign information of the multiplier quantity as a carry input for the least significant bit of the adder of each multiplier stage. In practice, it has been found to be necessary to produce a two's complement partial product in a more accurate manner in the course of digital computation of signal values while, at the same time, avoiding the introduction of unduly complex signal processing circuits. It has been found that the operations of truncation and two's complementing are non-commutative and therefore special steps must be taken depending on the order of performing operations in order to insure an accurate result. It should also be noted that Christopher et al proposed arrangements for sensing and utilizing "carry" signals occurring at the outputs of the various stages of the multiplier (adders) to control system signal gain and thereby prevent data "overflow". Specifically, the carry bits from a plurality of multiplier stages were summed by Christopher and Sprague in a common circuit and the resulting sum was taken to be indicative of "overflow" of the capacity of the arithmetic circuits. It was proposed by Christopher and Sprague that the gain of analog signal amplifier(s) preceding the FIR filter input be adjusted in response to the carry information to reduce the occurrence of such "overflow" conditions. The presence of that gain control capability has not been found to be required in an FIR filter in the general case.